1. Technical Field
The invention disclosed broadly relates to integrated circuit technology and more particularly relates to on chip monitoring of circuit characteristics for integrated circuit devices.
2. Background Art
FIG. 1 is a high level circuit schematic diagram of a typical signal path on an integrated circuit chip where an input signal is applied to an input driver, that signal being propagated along a low impedance conductor 10 to an output driver. The low impedance conductor 10 will have a variety of capacitive contributions CGX, which is the capacitance between field effect transistor (FET) gates and the chip substrate, CM1 which is the capacitance with respect to ground of first level aluminum conductor lines, and CM2 which is the capacitance with respect to ground of second level metal conductor lines. The signal propagation delay along the conductor 10 is a function of the magnitudes of CGX, CM1 and CM2, and the characteristics and the output impedance of the input driver and the delay characteristics of the output driver. FIG. 2 is a more detailed view of the typical signal path as was depicted in FIG. 1. The input driver is shown as a typical N channel depletion mode FET inverter circuit with the FET transistor Q1 being a depletion mode load device and the FET transistor Q2 being an enhancement mode active device, with the input terminal IN being connected to the gate of Q2 and the output terminal 26 being connected to the conductor 10. The effective resistance of Q1 is the output impedance of the input driver. The greater the magnitude of the output impedance of the input driver, the longer it will take for the drain voltage Vdd to provide a current flowing into the conductor 10 during rise time of the signal propagated on the conductor 10. The output driver shown in FIG. 2 comprises the push/pull connected pair of inverters consisting of a first inverter having the depletion mode load FET device Q3 and the enhancement mode active device Q4 and the second inverter consisting of the zero threshold FET device Q5 and the enhancement mode active device Q6. The conductor 10 applies the signal through the node 34 to the gate of the transistor Q4. The impedance of the depletion mode FET load device Q3 determines the speed with which the signal is propagated to the second inverter in the output driver. The signal is applied from the output node 35 to the gate of the natural threshold FET device Q5 and the node 34 applies the signal directly to the gate of the active enhancement mode FET device Q6. As a result, a positive going signal on the node 34 will result in a negative going signal at the output terminal OUT. The overall propagation delay from the input node IN to the input driver, over the conductor 10 to the output node OUT of the output driver is the signal propagation delay of a typical circuit on the integrated circuit chip.
Signal propagation delays can vary as a function of the process parameters which occurred during the fabrication of the integrated circuit chip. For example variations in the conductivity of the semiconductor substrate, the dopant concentration of the N-type diffusions in the substrate, variations in the thickness of the gate oxide layers and misregistrations in the photolithographic masks can result in changes in the resistance of the depletion mode FET load devices such as Q1 in the input driver. If the resistance in Q1 increases, then the signal propagation delay will be longer. If the magnitude of the resistance of Q1 decreases, then the signal propagation delay will be faster. Other variations in process parameters such as thick oxide insulator thickness, polyimide insulator thickness, metallized line widths, can influence the capacitance CM1 and CM2 for the conductor 10. If capacitance increases, then the signal propagation delay will increase. If capacitance decreases, then the signal propagation delay will decrease. Still further, if there are variations in the ion implantation concentration of dopants for the natural threshold FET device Q5, this will influence the signal propagation delay. If the threshold voltage for the FET device Q5 increases, this will increase the effective signal propagation delay, and vice versa.
Modern integrated circuits are designed with precise signal propagation delay characteristics. Oftentimes, circuits operating in parallel must have very closely matched propagation delay characteristics in order to operate properly. It is therefore important to be able to match integrated circuit chips by means of their propagation characteristics in order to have them operate as intended in such potential race conditions. It is also important to know the signal propagation delay characteristics for a circuit in order to know whether it will work in a particular application. By having an effective signal propagation delay monitor, integrated circuit chips can be sorted by their speed characteristic.
Reference will be briefly made to FIG. 3 which is a cross-sectional view of the physical structure for the conductor 10 which is a typical interconnection of circuit elements in an integrated circuit. In FIG. 3, the input node 26 for the conductor 10 can be an N-type diffusion in the P-type silicon substrate 20 which is connected through the oxide layer 28 by means of a via hole connection to the first level aluminum conductor line 30, which is referred to as the M1 layer. The conductor line 30 can have a connection through a via hole to the polycrystalline silicon conductor 24 which is part of a gate electrode for an N channel FET device 22 in the chip. The capacitance between the polycrystalline silicon gate 24 and the substrate 20 is referred to as CGX in the schematic diagram of FIG. 2. The capacitance between the first level metal conductor line 30 and the substrate 20 is referred to as CM1 in the schematic diagram of FIG. 2. Oftentimes, the integrated circuit will have two levels of metal conductor lines, the first M1 level lines running in a first direction and a second higher level M2 lines running in an orthogonal direction. As shown in the cross-sectional view of FIG. 3, a polyimide and silicon nitride layer 32 separates the lower M1 metal layer from an upper M2 metal layer and they are electrically interconnected through via hole connections. The M2 layer shown in FIG. 3 includes a conduction line 34 which forms a part of the conductor 10. The M2 layer 34 has a capacitance with respect to the substrate 20 which is referred to as CM2 in the schematic diagram of FIG. 2.